Self-aligned, trenchless mangetoresitive random-access memory (MRAM) structure with sidewall containment of MRAM structure

ABSTRACT

This invention pertains to a method of fabricating a trenchless MRAM structure and to the resultant MRAM structure. The MRAM structure of the invention has a pinned layer formed within protective sidewalls formed over a substrate. The protective sidewalls facilitate formation of the MRAM structure by a self-aligning process.

FIELD OF THE INVENTION

[0001] This invention generally relates to a method of fabricating anMRAM structure, and more particularly to an MRAM structure that has apinned layer formed above an insulating layer and within a protectivesidewall.

BACKGROUND OF THE INVENTION

[0002] Integrated circuit designers have always sought the idealsemiconductor memory: a device that is randomly accessible, can bewritten or read very quickly, is nonvolatile, but indefinitelyalterable, and consumes little power. Magnetoresistive random accessmemory (MRAM) technology has been increasingly viewed as offering allthese advantages.

[0003] A magnetic memory element has a structure which includes magneticlayers separated by a non-magnetic layer. Information can be read as a“1” or a “0” as directions of magnetization vectors in these magneticlayers. Magnetic vectors in one magnetic layer are magnetically fixed orpinned, while the magnetic vectors of the other magnetic layer are notfixed so that the magnetization direction is free to switch between“parallel” and “antiparallel” states relative to the pinned layer. Inresponse to parallel and antiparallel states, the magnetic memoryelement represents two different resistance states, which are read bythe memory circuit as either a “1” or a “0.” It is the detection ofthese resistance states for the different magnetic orientations thatallows the MRAM to read and write information.

[0004] In standard MRAM processing, there are certain sensitivitiesrelated to the use of optical photolithography. Typically, the freemagnetic layer is patterned separately from a previously depositedcopper interconnect line and the pinned magnetic layer, which rests overit. This separate patterning requires a photo-step, in whichregistration is critical for placement of the free layer over the pinnedlayer.

[0005] Spin etching is typically used to form the pinned layer. Spinetching causes the pinned layer to be “dished” or recessed in the centerto a greater degree than the more exterior regions. This recessed shapeis desirable because it is thought to cause more of the electromagneticfield to be directed at the free magnetic layer, thereby reducing thecurrent needed to change the state of the free layer. Spin etching isnotoriously non-uniform as it relates to the variations between thecenter and the outer regions of the wafer. Additionally, there areproblems with lopsidedness at the trailing edge of the spin caused bythis process.

[0006] It would be desirable to have a method of fabricating the MRAMstructure whereby the structure is formed in a more accurate andreliable way. Sidewall protection of the MRAM structure, prevention ofcopper migration, and accurate definition of the structure are allcharacteristics desired to be improved. Additionally, processing of theMRAM structure without need for spin etching so as to achieve a moreuniform structure across the wafer would also be advantageous.

SUMMARY OF THE INVENTION

[0007] This invention provides a method of fabricating an MRAMstructure. The MRAM structure of the invention does not have the pinnedlayer recessed within a trench, but instead forms it above an insulatinglayer. The method provides a sidewall protection for the bottom magneticlayer of the MRAM structure and insures a more reliable structure, whichalso allows definition of the MRAM stack by a self-aligning process. Bythis self-aligned process, the bottom portion of the MRAM stack,incorporating the bottom magnetic layer, is defined in a single etchingstep and the top portion, incorporating the top magnetic layer, isdefined above the bottom magnetic layer in another single, self-alignedetching step, which positions the top magnetic layer over the bottommagnetic layer.

[0008] This process allows for the fabrication of MRAM structureswithout employing trench process technology. It eliminates many of thesensitivities associated with optical photolithography as well as theprocess variabilities associated with spin etching of the recess regionfor the pinned layer. Finally, it allows for accurate control of the topmagnetic layer in its positioning over the bottom magnetic layer so asto improve the electrical characteristics of the MRAM.

[0009] These and other features and advantages of the invention will bemore clearly understood from the following detailed description of theinvention which is provided in connection with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. I is an illustration of an intermediate stage of processingof the MRAM device according to the invention;

[0011] FIG. II is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. I;

[0012] FIG. III is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. II;

[0013] FIG. IV is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. III;

[0014] FIG. V is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. IV;

[0015] FIG. VI is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. V;

[0016] FIG. VII is an illustration of a stage of processing of the MRAMdevice according to the invention, subsequent to the stage illustratedin FIG. VI;

[0017] FIG. VIII is a cutaway perspective view of multiple MRAM devicesillustrating the interconnect between top magnetic layer islands inrelation to underlying bottom magnetic layer lines; and

[0018] FIG. IX is an illustration of a processor-based system having amemory circuit and incorporating an MRAM device fabricated in accordancewith the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0020] The terms “substrate” and “wafer” are used interchangeably in thefollowing description and may include any semiconductor-based structure.The structure should be understood to include silicon, silicon-oninsulator (SOI), silicon-on-sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor need not be silicon-based. The semiconductor could besilicon-germanium, germanium, or gallium arsenide. When reference ismade to the substrate in the following description, previous processsteps may have been utilized to form regions or junctions in or over thebase semiconductor or foundation.

[0021] The term “metal” is intended to include not only elemental metal,but metal with other trace metals or in various alloyed combinationswith other metals as known in the semiconductor art, as long as suchalloy retains the physical and chemical properties of the metal. Theterm “metal” is also intended to include conductive oxides of suchmetals.

[0022] No particular order is required for the method steps describedbelow, with the exception of those logically requiring the results ofprior steps. Accordingly, while many of the steps discussed below arediscussed as being performed in an exemplary order, this order may bealtered.

[0023] The invention provides a method of forming an MRAM structure thatdoes not require the pinned layer, that is, the bottom magnetic (M1)layer, to be recessed within a trench. Additionally, this method resultsin a protective sidewall for the MRAM structure. Such a protectivesidewall adds increased reliability by preventing the migration ofcopper out of the M1 interconnect line, that is, the digit line, andalso allows the MRAM stack to be accurately defined during processing.Further, by using the process of the invention, many of thesensitivities associated with optical photolithography are eliminated,as are the processing variabilities associated with spin etching of arecess region for the pinned layer. Finally, the method of the inventionallows for accurate control of the top magnetic layer (M2) size andpositioning over the M1 layer so as to improve the electricalcharacteristics of the MRAM structure.

[0024] Referring now to the drawings, where like elements are designatedby like reference numerals, FIG. I depicts a cross-section of an MRAMmemory cell during processing at an intermediate stage wherein asemiconductor layer 8, a layer 10 having CMOS access and logictransistors over the semiconductor layer 8, and layer of insulatingmaterial 11, preferably TEOS or CVD nitride, are provided. Theinsulating layer 11 should be about 5000 Angstroms thick. CMOS accesstransistors (not shown) can be fabricated over the semiconductor layer 8and within layer 10 in the regions around and under the periphery of theMRAM array to control the functioning (reading and writing) of the MRAMdevices to be fabricated by the process of this invention. Othertransistors, such as logic or decoder transistors are fabricated in thissame layer 10 but under the MRAM array. Such a configuration of the MRAMtransistors conserves valuable space on the wafer. All MRAM fabricationsteps discussed hereafter occur over the layer 10 within which the CMOStransistor structures are formed and the planar insulating layer 11surface formed over theses structures. Layers 8, 10, and 11 can beconsidered to be a substrate for further processing steps.

[0025] An oxide layer 12 is formed over the insulating layer 11. Thismay be accomplished as known in the art by any convenient means, such asby chemical vapor deposition (CVD). This oxide layer 12 is patternedwith photoresist mask 14 to prevent the etching of regions that will notbe removed until later processing steps. The protected oxide layer 12regions will serve as separators for the MRAM stacks 32 during the firststage of fabrication.

[0026] Referring now to FIG. II, portions of the oxide layer 12 areremoved using photoresist mask 14 to expose the underlying insulatinglayer 11. This may be accomplished in multiple ways after thephotoresist mask 14 is developed over those portions not to be removed.A spacer oxide etch plus a facet etch can be used; a spacer etch can beused; and use of an oxide implant into an non-oxidized layer followed bya selective wet etch to remove the oxidized regions can be used as well.The photoresist 14 is also removed from over the remaining sections ofthe oxide layer 12. This step leaves the oxide layer 12 over portions ofthe substrate 10 that are between the future MRAM stacks 32 (see FIG.VII) as shown in FIG. II. These remaining sections of the oxide layer 12are intended to provide contours to the upper surface of the wafer.

[0027] Referring to FIG. III, a series of layers are next deposited overthe insulating layer 11 and remaining oxide layer 12 to form the bottomportion 38 (see FIG. IV) of the MRAM stack 32 (see FIG. VII). The firstof these layers is an insulating nitride layer 16. The nitride layer 16can be formed by CVD, PECVD, or ALD, and should be thick enough to beable to form sidewalls, less than 200 Å should be sufficient. Otherinsulating layers can be alternatively used for layer 16, such asaluminum oxide, silicon oxide, or aluminum nitride. Over this nitridelayer 16 is deposited a layer of tantalum 18. The tantalum layer 18 isan adhesion, barrier, and etch stop layer, and can be sputter depositedto a thickness of about 100 Å. Next is deposited a layer of copper 20over the tantalum layer 18. This copper layer 20 forms an interconnectline and is the current carrier between the MRAM pinned layer (M1 22)and associated CMOS circuitry in the underlying CMOS layer 10, and itcan be formed by electroplating or sputtering, and should be about 2000Å thick. This copper layer 20 interconnect can be used as the digitline, or bit line, for the MRAM device. Over the copper layer 20 isdeposited another barrier layer 19 comprising tantalum. This barrierlayer can be about 20-400 Å thick. This barrier layer 19 separates thecopper of the digit line from the subsequently formed layers. Over theselayers 16, 18, 19, 20 is next deposited a seed layer 21 for the bottommagnetic layer region. The seed layer may comprise NiFe and should beabout 10-100 Å thick. This seed layer 21 enables proper crystal growthof the next deposited anti-ferromagnetic layer 23. An anti-ferromagneticlayer 23 is formed over the seed layer to enable the pinning of thebottom magnetic layer. The anti-ferromagnetic layer 23 may be FeMn andshould be about 10-100 Å thick. Over this anti-ferromagnetic layer 23 isformed the first magnetic layer (M1) 22.

[0028] These layers 16, 18, 19, 20, 21, 23, 22 are deposited in aconformal manner, as shown in FIG. III, so that at its highest pointrelative to the underlying substrate 10, the nitride layer 16 depositedover and on the lateral sides of the remaining portions of the oxidelayer 12 is at a higher elevation than the lowest portion of the M1layer 22, relative to the underlying substrate.

[0029] The nitride layer 16 is a protective and containment layer. Itallows for part of the self-alignment of subsequent process stepsbecause it provides a differential layer to allow a wet removal of theoxide at a later stage of processing, it acts as a stop layer for theCMP process described below; it is a containment barrier against sidedamage to the MRAM structure and helps prevent the migration of thecopper from the copper layer 20 forming the digit lines.

[0030] The M1 layer 22 may be deposited by any convenient method, suchas by sputtering or evaporation techniques, and depending on thematerials used, should have a thickness of about 10-100 Å. The M1 layer22 may be one or more layers of any of a variety of materials with goodmagnetic properties, such as nickel iron cobalt (NiFeCo) alloy, or anysimilar compounds or alloys. This first magnetic layer 22 is preferablynickel iron (NiFe). The M1 layer 22 will form the pinned magnetic layer,meaning that the magnetic orientation of the layer is fixed during theaccessing of the M1 layer 22 during MRAM operation. This M1 layer 22 ispinned because of its association with the underlying anti-ferromagneticlayer 23, creating a singularly-oriented fixed magnetic field for thisM1 layer 22.

[0031] Referring to FIG. IV, the just deposited layers 16, 18, 19, 20,21, 23, 22 and the underlying remaining oxide layer 12 are patterned andetched so that the regions of the layers 16, 18, 19, 20, 21, 23, 22 overthe remaining oxide layer 12 and the oxide layer 12 itself are removedand the underlying insulating layer 11 is exposed. This may beaccomplished by etching with HF acid. The layers 16, 18, 19, 20, 21, 23,22 should remain over the insulating layer 11 where the oxide layer 12was first removed, as described in relation to FIG. II, so that thelayers remain over the nitride bottom layer 16 and within the nitridesidewalls 24 created by the selective removal of the unwanted portionsof the layers. The layers should next be polished by CMP (chemicalmechanical polishing) using the nitride layer 16 as the stop layer toform stacks of layers for the MRAM bottom portion 38 as shown in FIG.IV. This resulting structure should be such that the bottom nitridelayer 16 forms complete sidewalls 24 for the entire height of, and aremaining bottom portion of the layer 16 for the length of the bottom ofthe MRAM structure as shown in FIG. IV and VIII. Also, the uppermostfirst M1 layer 22 of the structure should incorporate a recessed region26, as shown in FIG. IV and VIII, which is below the top of the nitridesidewalls 24. This recessed region 26 of the M1 layer 22 is a naturaloccurrence of the conformal deposition of the layers 16, 18, 19, 20, 21,23, 22 and the CMP process, and as discussed above in relation to FIG.III, was made possible because the nitride layer 16 was formed at amaximum height which was above this recessed region 26 of the M1 layer22. Forming the recessed region 26 by this method eliminates the processvariables associated with spin etching of a recess for the pinned layeras used in the prior art, and therefore, results in a more uniformstructure. The nitride sidewall 24 provides structure reliability bypreventing bridging between structures, which could occur in the priorart because of the reliance on anisotropic etching to accomplish deviceseparation. The sidewall 24 also confines the copper layer 20 andprevents copper migration from the digit line into any surroundinglayers. Using the nitride sidewall 24 technique is a more accuratemethod of defining an MRAM stack 32 because the initial oxide pattern,which contributes to the sidewall 24 formation, is a single criticalalignment at a IF size that is not registration sensitive.

[0032] Referring to FIG. V, a non-magnetic layer 28 is next depositedconformally over the layer stacks and the insulating layer 11. Thisnon-magnetic layer 28 can be aluminum oxide (Al₂O₃), or another suitablematerial with equivalent characteristics, and can be formed bydepositing an aluminum film over the substrate 10 and layer stacks, andthen oxidizing the aluminum film by an oxidation source, such as RFoxygen plasma. This non-magnetic layer 28 should be about 5-25 Å thick.As stated this layer is non-magnetic and serves as tunnel oxide,electron sharing or a barrier layer for the magnetic layers during MRAMoperation. The aluminum oxide non-magnetic layer 28 acts as an electronsharing layer when the magnetic orientation of the two magnetic layersis opposite, causing them to attract. Electrons are shared through thevalence bands of the non-magnetic, nonconductive layer 28, allowing forelectron migration. However, when the magnetic orientation of the twomagnetic layers is alike, causing them to repulse, this aluminum oxidelayer 28 provides an effective barrier layer preventing electronmigration.

[0033] Over this non-magnetic layer 28 a second magnetic layer (M2) 30is conformally deposited. This M2 layer 30 forms the free layer of theMRAM device 32. The M2 layer 30 can be comprised of one or more layersof materials similar to those of the M1 layer 22, preferably NiFe andshould also be about 10-100 Å thick. Over the M2 layer 30 is formed acapping and barrier layer 31 to provide oxidation and diffusion barrierprotection. This layer 31 can be comprised of tantalum and should beabout 20-400 Å thick.

[0034] As opposed to the M1 layer 22 (the pinned layer), the M2 layer 30will not have a fixed magnetization orientation and will be free toshift this orientation, and thus acts as the element for determining thestored value of a memory cell. It is the shifting of the magneticorientation of the M2 layer 30 that allows the MRAM device to store dataas one of two logic levels. This is accomplished by changing the currentflow in the sense line of the M2 layer 30 to be in one direction or theopposite direction, thereby causing the related magnetic fields toreverse. Oppositely directed current flows for the M2 30 layer, resultin magnetic fields of opposite polarity, which interact with the pinnedmagnetic field of the M1 22 layer so that either a “0” or a “1” is readby the sense line as different resistances.

[0035] Referring to FIG. VI, the MRAM stacks 32 are now patterned overthe substrate. This is a self-aligning process. Another photoresist mask15 is formed and patterned over the capping and barrier layer 31 and theM2 layer 30 and the remaining layers 16, 18, 19, 20, 21, 23, 22 of thebottom portion 38 of the MRAM stack 32. This photoresist mask 15 definesdiscrete and isolated regions of M2 layer 30 and non-magnetic layer 28over the M1 layer 22 (capped with layer 31).

[0036] Referring to FIG. VII, layer 31, the M2 layer 30 and thenon-magnetic layer 28 are next removed to expose the underlyinginsulating layer 11 and portions of the bottom portion 38 of the MRAMstacks 32. This may be accomplished by selectively etching layer 31, theM2 layer 30 and the aluminum oxide non-magnetic layer 28 over theunderlying materials to leave discrete islands 34 of layers 31, 30, and28 over the rows of the bottom portions 38 of the MRAM stacks 32. Thenthe photoresist mask 15 is removed and the islands 34 over the MRAMstacks 32 are polished by CMP to form the MRAM stacks 32 shown in FIG.VII.

[0037] By the method of the invention, the M2 layer 30 can be accuratelycontrolled in its positioning over and in relation to the M1 layer 22 bythe masking and etching steps described in relation to FIG. VI and FIG.VII. This accurate control improves the electrical characteristics ofthe MRAM device. Because of the differences in characteristics betweenthe magnetic material and the non-magnetic material and the nitridesidewall 24, the outer edges of the M2 layer 30 can be adjusted to beoutside or inside those of the M1 layer 22, without the need formultiple reticles, depending on the desired application. The inventionalso reduces the lateral direction sensitivity in positioning the M2layer 30 over the M1 layer 22 because the completed MRAM stack 32,including the already formed underlying structure containing the M1layer 22 and the now formed M2 layer 30, is defined in a singleself-aligning step when the M2 layer 30 and the non-magnetic layer 28are etched to leave those layers 28, 30 only over the already defined M1layer 22.

[0038] Referring to FIG. VIII, after formation of the MRAM stack 32 theM2 layer 30 and the non-magnetic layer 28 (and the capping/barrier layer31) islands 34 on the top of the MRAM stack 32 are isolated bydepositing a layer of dielectric material 40 over the islands 34, theexposed rows of the bottom portion 38 of the MRAM stacks 32, andunderlying wafer as shown. The dielectric layer 40 can be TEOS or CVDnitride.

[0039] The capping and barrier layer 31 of each island 34 is re-exposedby etching through the dielectric layer 40 to allow for the formation ofinterconnect lines. The M2 layer 30 of the island 34 is connected(through layer 31) to an upper conductive interconnect line 36, which isthe sense line or wordline, formed orthogonal to the underlying bottomportion 38 of the MRAM stack 32. The M2 layer 30 of the island 34 isthereby connected to the M2 layer 30 of other islands 34 over other M1layers 22 by this upper conductive interconnect line 36. This upperconductive interconnect line 36 is preferably copper and about 2000 Åthick. Next, a dielectric layer (not shown) is blanket deposited overthe MRAM stacks 32 and the upper conductive interconnect lines 36. Thisdielectric layer is polished to form a planarized surface over the upperconductive lines 36 (not shown for illustrative purposes). Thisdielectric layer can also be TEOS or CVD nitride.

[0040] As stated, the bottom portion 38 of each MRAM stack 32, includingthe nitride layer 16, the tantalum layer 18, the copper layer 20, andthe M1 layer 22 run contiguously under the M2 layer islands 34,connecting multiple M2 layer islands 34 in rows orthogonal to the upperconductive interconnect lines 36. All of the M2 layer islands 34 notconnected on the same upper conductive interconnect line 36 or on thesame M1 layer 22 are electrically isolated from each other by thedielectric layer 40 deposited over the entire wafer. The underlyingbottom portions 38 of each MRAM stack 32 are also electrically isolatedfrom other MRAM stacks 32 by this dielectric layer 40.

[0041] After the formation of the MRAM stacks 32, the M2 layer islands34, the isolation of the MRAM stacks 32 and the M2 layer islands 34, andthe formation of the upper conductive interconnect lines 36, MRAMprocessing continues as known in the art.

[0042] As already discussed, the MRAM devices are connected tocontrolling transistors. These controlling transistors (not shown) arefabricated within the CMOS layer 11 and can be located in the peripheryaround the MRAM array. There can be contacts from the copperinterconnect lines 20, 36, the digit and sense lines, for the M1 and M2layers 22, 30; one contact for each copper interconnect. Each contact isconnected to at least one controlling transistor in the periphery, whichis used to turn the memory devices on or off. These transistors can beformed by standard CMOS processing as known in the art. To conservewafer space, at least some of the accompanying transistors, such asthose for logic and decoding, can be located below the MRAM array.

[0043] This invention provides the ability to form MRAM devices asdescribed above with high levels of vertical integration. This can beaccomplished by forming a plurality of similar stacks and connects inthe vertical direction. The MRAM stacks 32 and connects, as describedabove in relation to FIGS. I-VIII, may be duplicated a plurality oftimes in the vertical direction, thereby saving valuable wafer space.These additional levels of integration can be formed over the dielectriclayer formed over and around the MRAM device upper interconnect lines36, described above. The second level of integration is formed by thesame process described above in relation to FIGS. I-VIII over thisdielectric layer.

[0044] FIG. IX illustrates a processor system (e.g., a computer system),with which a memory having an MRAM memory device as described above maybe used. The processor system comprises a central processing unit (CPU)102, a memory circuit 104, and an input/output device (I/O) 100. Thememory circuit 104 contains an MRAM, and possibly another memory device,including devices constructed in accordance with the present invention.Also, the CPU 102 may itself be an integrated processor, in which boththe CPU 102 and the memory circuit 104 may be integrated on a singlechip, so as to fully utilize the advantages of the invention. Thisillustrated processing system architecture is merely exemplary of manydifferent processor system architecture with which the invention can beused.

[0045] The above description and accompanying drawings are onlyillustrative of exemplary embodiments, which can achieve the featuresand advantages of the present invention. It is not intended that theinvention be limited to the embodiments shown and described in detailherein. The invention can be modified to incorporate any number ofvariations, alterations, substitutions or equivalent arrangements notheretofore described, but which are commensurate with the spirit andscope of the invention. The invention is only limited by the scope ofthe following claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming an MRAM device, comprising:forming freestanding insulating sidewalls over a substrate to define aprotective region bounded by said sidewalls, said sidewalls being formedabove the uppermost level of said substrate; forming a bottom magneticlayer within said protective region; and forming a top magnetic layerover a region of said bottom magnetic layer.
 2. The method of claim 1,wherein said freestanding insulating sidewalls are interconnected alongtheir length by a bottom insulating layer between said sidewalls.
 3. Themethod of claim 2, wherein the act of forming said freestandinginsulating sidewalls and said bottom insulating layer comprises: forminga first insulating layer over said substrate and over at least twospaced sacrificial regions formed over said substrate, said sacrificialregions being substantially parallel to each other, extendinglongitudinally across said substrate, and having substantially verticalsidewalls, wherein said insulating sidewalls are formed on saidsubstantially vertical sidewalls of said sacrificial regions and saidbottom insulating layer is formed between said sacrificial regions; andremoving said at least two sacrificial regions and the portion of saidfirst insulating layer formed thereover to leave said freestandinginsulating sidewalls and said bottom insulating layer between saidfreestanding insulating sidewalls, said freestanding insulatingsidewalls and said bottom insulating layer each formed of said firstinsulating layer.
 4. The method of claim 3, wherein the act of formingsaid bottom magnetic layer comprises: forming a seed layer over saidfirst insulating layer and within said protective region; forming ananti-ferromagnetic layer over said seed layer and within said protectiveregion; and forming said bottom magnetic layer over saidanti-ferromagnetic layer and within said protective region, wherein saidbottom magnetic layer has an upper recessed region.
 5. The method ofclaim 4, further comprising: forming a first barrier layer over saidfirst insulating layer and within said protective region, wherein saidfirst insulating layer comprises a nitride; forming a conducting layerover said barrier layer and within said protective region; forming asecond barrier layer over said conducting layer and within saidprotective region, wherein said seed layer is formed over said secondbarrier layer; removing the portions of said barrier layers, saidconducting layer, said seed layer, said anti-ferromagnetic layer, andsaid bottom magnetic layer that overly said sacrificial regionssimultaneously with said removing of said sacrificial regions and saidportion of said first insulating layer formed thereover; and polishingthe not removed portions of said first insulating layer, said firstbarrier layer, said conducting layer, said second barrier layer, saidseed layer, said anti-ferromagnetic layer, and said bottom magneticlayer using said first insulating layer as a stop layer for saidpolishing.
 6. The method of claim 5, wherein said act of removingportions of said first insulating layer, said first barrier layer, saidconducting layer, said second barrier layer, said seed layer, saidanti-ferromagnetic layer, said bottom magnetic layer, and saidsacrificial regions, comprises etching.
 7. The method of claim 5,wherein said first and second barrier layers comprise tantalum.
 8. Themethod of claim 5, wherein said conducting layer comprises copper. 9.The method of claim 5, wherein said seed layer comprises nickel iron.10. The method of claim 5, wherein said anti-ferromagnetic layercomprises iron manganese
 11. The method of claim 5, wherein said bottommagnetic layer comprises nickel iron.
 12. The method of claim 5, whereinsaid sacrificial regions comprise an oxide.
 13. The method of claim 5,wherein the act of forming said top magnetic layer comprises: forming alayer of non-magnetic material over said bottom magnetic layer andwithin said upper recessed region of said bottom magnetic layer; formingsaid top magnetic layer over said layer of non-magnetic material;forming a third barrier layer over said top magnetic layer; and removingportion of said layer of non-magnetic material, a portion of said topmagnetic layer, and a portion of said third barrier layer to leave anisland of said non-magnetic material, said top magnetic layer, and saidthird barrier layer over said region of said bottom magnetic layer. 14.The method of claim 13, wherein the act of removing a portion of saidlayer of non-magnetic material, a portion of said top magnetic layer,and a portion of said third barrier layer comprises etching.
 15. Themethod of claim 13, wherein said layer of non-magnetic materialcomprises aluminum oxide.
 16. The method of claim 13, wherein said topmagnetic layer comprises nickel iron.
 17. The method of claim 13,wherein said third barrier layer comprises tantalum.
 18. The method ofclaim 13, further comprising forming a conductive interconnect line oversaid island of said non-magnetic material, said top magnetic layer, andsaid third barrier layer, said conductive interconnect line beingorthogonal to said bottom magnetic layer.
 19. The method of claim 18,wherein said conductive interconnect line is a wordline and saidconducting layer is a bit line.
 20. The method of claim 18, furthercomprising forming a dielectric layer over said conductive interconnectline, said first magnetic layer, and said substrate.
 21. A method offorming an MRAM memory device, comprising: forming a freestandingstacked structure above a substrate, said stacked structure comprisingnitride sidewalls and a nitride bottom layer interconnecting saidsidewalls, a conducting layer within said nitride sidewalls, and a firstmagnetic layer within said nitride sidewalls and over said conductinglayer; forming a non-magnetic layer over a region of said stackedstructure; and forming a second magnetic layer over said non-magneticlayer.
 22. The method of claim 21, wherein the act of forming saidfreestanding stacked structure comprises: forming raised oxide layerregions over portions of said substrate, wherein portions of saidsubstrate between said raised oxide layer regions are exposed; forming anitride layer over said raised oxide layer regions and said exposedportions of said substrate; forming said conducting layer over saidnitride layer; forming said first magnetic layer over said conductinglayer; etching to expose said substrate where under said oxide layerregions to form said freestanding stacked structure, which includes saidnitride sidewalls, a remaining bottom nitride layer between saidsidewalls, a remaining conductive layer over said remaining bottomnitride layer, and a remaining first magnetic layer over said remainingconductive layer, said first magnetic layer having an upper recessedregion; and polishing said freestanding stacked structure using saidnitride sidewalls as a stop layer.
 23. The method of claim 22, whereinact of polishing said freestanding stacked structure does not removesaid upper recessed region of said first magnetic layer.
 24. The methodof claim 22, wherein said act of forming said freestanding stackedstructure further comprises: forming a first barrier layer within saidnitride sidewalls and over said nitride bottom layer, wherein saidconducting layer is formed over said first barrier layer; forming asecond barrier layer within said nitride sidewalls and over saidconducting layer; forming a seed layer within said nitride sidewalls andover said second barrier layer; and forming an anti-ferromagnetic layerwithin said nitride sidewalls and over said seed layer, wherein saidfirst magnetic layer is formed over said anti-ferromagnetic layer;wherein said oxide layer regions, said nitride layer, said first andsecond barrier layers, said conductive layer, said seed layer, saidanti-ferromagnetic layer and said first magnetic layer are etchedsimultaneously to expose said substrate and form said freestandingstacked structure.
 25. The method of claim 24, further comprisingpolishing said stacked structure using said nitride sidewalls as an etchstop layer.
 26. The method of claim 25, wherein said forming of saidnon-magnetic layer and said second magnetic layer comprise: forming saidnon-magnetic layer over said freestanding stacked structure and saidsubstrate; forming said second magnetic layer over said non-magneticlayer; removing portions of said second magnetic layer and saidnon-magnetic layer from over said substrate and said stacked structure,wherein said second magnetic layer and said non-magnetic layer remainover said region of said stacked structure, and wherein said removing ofsaid second magnetic layer and said non-magnetic layer leaves an islandof said second magnetic layer and said non-magnetic layer over saidstacked structure.
 27. The method of claim 26, further comprising:forming a third barrier layer over said second magnetic layer, a portionof which is removed simultaneously with said second magnetic layer,wherein said act of removing portions of said third barrier layer, saidsecond magnetic layer and said non-magnetic layer comprises etching. 28.The method of claim 24, wherein said first and second barrier layerscomprise tantalum.
 29. The method of claim 24, wherein said conductinglayer comprises copper.
 30. The method of claim 24, wherein said seedlayer comprises nickel iron.
 31. The method of claim 24, wherein saidanti-ferromagnetic layer comprises iron manganese.
 32. The method ofclaim 24, wherein said first magnetic layer comprises nickel iron. 33.The method of claim 26, wherein said non-magnetic layer comprisesaluminum oxide.
 34. The method of claim 26, wherein said second magneticlayer comprises nickel iron.
 35. The method of claim 27, wherein saidthird barrier layer comprises tantalum.
 36. The method of claim 27,further comprising forming a conductive interconnect line over saidthird barrier layer, said conductive interconnect line being orthogonalto said stacked structure.
 37. The method of claim 36, wherein saidconductive interconnect line is a wordline and said conducting layer isa bit line.
 38. The method of claim 36, further comprising forming adielectric layer over said conductive interconnect line.
 39. A method offorming a semiconductor device, comprising: forming a plurality oflayers of MRAM cells over a substrate, the forming of at least one ofsaid layers of MRAM cells comprising: forming at least one firstfreestanding stacked structure over a substrate, said at least one firstfreestanding stacked structure having first nitride sidewalls, a firstnitride bottom layer interconnecting said first nitride sidewalls, andthe following layers over said first nitride bottom layer and withinsaid nitride sidewalls: a first barrier layer over said first nitridebottom layer, a conducting layer over said first barrier layer, a secondbarrier layer over said conducting layer, a seed layer over said secondbarrier layer, an anti-ferromagnetic layer over said seed layer, and abottom magnetic layer and over said anti-ferromagnetic layer, saidbottom magnetic layer having a recessed region; forming a firstnon-magnetic layer over a first region of said bottom magnetic layer ofsaid at least one first freestanding stacked structure and within saidrecessed region of said bottom magnetic layer; forming a first topmagnetic layer over said first non-magnetic layer; forming a thirdbarrier layer over said first top magnetic layer; and forming a firstconductive interconnect line over said third barrier layer, wherein saidfirst conductive interconnect line is orthogonal to said at least onefirst freestanding stacked structure.
 40. The method of claim 39,wherein the act of forming said at least one first freestanding stackedstructure comprises: forming substantially parallel first raised oxidelayer regions over portions of a substrate, wherein portions of saidsubstrate between said first raised oxide layer regions are exposed;forming a first nitride layer over said first raised oxide layer regionsand said exposed portions of said substrate; forming said first barrierlayer over said first nitride layer; forming said conducting layer oversaid first barrier layer; forming said second barrier layer over saidconducting layer; forming said seed layer over said second barrierlayer; forming said anti-ferromagnetic layer over said seed layer;forming said first bottom magnetic layer over said anti-ferromagneticlayer; etching to expose said substrate where under said first oxidelayer regions to form said at least one freestanding stacked structure;and polishing said at least one freestanding stacked structure usingsaid first nitride sidewalls as a stop layer, so as to leave saidrecessed region in said first bottom magnetic layer.
 41. The method ofclaim 40, further comprising: forming a dielectric layer over said firstconductive interconnect line and said substrate; and forming at leastone second layer of MRAM cells over said dielectric layer.
 42. Themethod of claim 40, wherein said first and second barrier layerscomprise tantalum.
 43. The method of claim 40, wherein said conductinglayer comprises copper.
 44. The method of claim 40, wherein saidconductive interconnect line comprises copper.
 45. The method of claim40, wherein said seed layer comprises nickel iron.
 46. The method ofclaim 40, wherein said anti-ferromagnetic layer comprises ironmanganese.
 47. The method of claim 40, wherein said first bottommagnetic layer comprises nickel iron.
 48. The method of claim 40,wherein said first non-magnetic layer comprises aluminum oxide.
 49. Themethod of claim 40, wherein said first top magnetic layer comprisesnickel iron.
 50. The method of claim 40, further comprising: forming atleast one second freestanding stacked structure adjacent to andsubstantially parallel to said first freestanding stacked structure,wherein said second freestanding stacked structure comprises identicallayers as said first freestanding stacked structure, wherein said firstconductive interconnect line is over said third barrier layer of eachsaid freestanding stacked structure and connects said first and saidsecond freestanding stacked structures.
 51. The method of claim 50,wherein said first conducting layers of said first and secondfreestanding stacked structures are bit lines and said first conductiveinterconnect line is a wordline.
 52. The method of claim 50, whereinsaid method is repeated over a dielectric layer formed over said firstand second freestanding stacked structures, said conductive interconnectline, and said substrate.
 53. A method of forming an MRAM device,comprising: forming at least two spaced oxide regions over a substrate,said at least two spaced oxide regions having substantially verticalsidewalls and being substantially parallel to one another; forming anitride layer over said at least two spaced oxide regions and saidsubstrate, wherein said nitride layer is formed on said substantiallyvertical sidewalls of said at least two spaced oxide regions; forming afirst barrier layer over said nitride layer; forming a conducting layerover said first barrier layer; forming a second barrier layer over saidconducting layer; forming a seed layer over said second barrier layer;forming an anti-ferromagnetic layer over said seed layer; forming abottom magnetic layer over said anti-ferromagnetic layer; exposing saidsubstrate under said at least two spacer oxide regions by etching,thereby forming nitride sidewalls comprising remaining said nitridelayer, wherein said sidewalls partially surround said first barrierlayer, said conducting layer, said second barrier layer, said seedlayer, said anti-ferromagnetic layer, and said bottom magnetic layer;polishing said bottom magnetic layer, said anti-ferromagnetic layer,said seed layer, said second barrier layer, said conducting layer, saidfirst barrier layer, and said nitride layer, using said nitridesidewalls as a stop layer, so that said bottom magnetic layer maintainsa recessed region in an upper portion thereof; forming a non-magneticlayer over said bottom magnetic layer and said substrate; forming a topmagnetic layer over said non-magnetic layer; forming a third barrierlayer over said top magnetic layer; etching said non-magnetic layer,said top magnetic layer and said third barrier layer so as to leaveislands of said non-magnetic layer, said top magnetic layer, and saidthird barrier layer over regions of said bottom magnetic layer;polishing said third barrier layer; forming a dielectric layer over saidthird barrier layer and said substrate; exposing tops of said islandsthrough said dielectric layer; and forming conductive interconnect linesover said islands, wherein said conductive interconnect lines areorthogonal to said bottom magnetic layer.
 54. The method of claim 53,wherein said barrier layers comprise tantalum.
 55. The method of claim53, wherein said conducting layer comprises copper.
 56. The method ofclaim 53, wherein said seed layer comprises nickel iron.
 57. The methodof claim 53, wherein said anti-ferromagnetic layer comprises ironmanganese.
 58. The method of claim 53, wherein said bottom magneticlayer comprises nickel iron.
 59. The method of claim 53, wherein saidnon-magnetic layer comprises aluminum oxide.
 60. The method of claim 53,wherein said top magnetic layer comprises nickel iron.
 61. The method ofclaim 53, wherein said conductive interconnect lines comprise copper.62. The method of claim 53, wherein said conductive interconnect linesare wordlines and said conducting layer is a bit line.
 63. The method ofclaim 53, wherein said method is repeated in the vertical directionafter forming a dielectric layer over said conductive interconnect linesand polishing said dielectric layer.
 64. An MRAM device, comprising: asubstrate; an insulating layer over said substrate, said insulatinglayer comprising sidewalls and a bottom portion between said sidewalls,said insulating layer being over the uppermost portion of saidunderlying substrate; a first conductive layer over said bottom portionof said insulating layer and between said sidewalls; a first magneticlayer over said conductive layer and between said sidewalls; and asecond magnetic layer over a region of said first magnetic layer. 65.The MRAM device of claim 64, further comprising: a first barrier layerover said bottom insulting layer and between said sidewalls, whereinsaid first conductive layer is over said first barrier layer; a secondbarrier layer over said first conductive layer; a seed layer over saidsecond barrier layer; and an anti-ferromagnetic layer over said seedlayer, wherein said first magnetic layer is over said anti-ferromagneticlayer.
 66. The MRAM device of claim 65, wherein said first magneticlayer has an upper recess in a portion thereof.
 67. The MRAM device ofclaim 66, further comprising: a non-magnetic layer over said region ofsaid first magnetic layer, wherein said non-magnetic layer is at leastpartially within said upper recess of said first magnetic layer and saidsecond magnetic layer is over said non-magnetic layer; a third barrierlayer over said second magnetic layer; and a second conductive layerover said third barrier layer and orthogonal to said first conductivelayer.
 68. The MRAM device of claim 67, wherein said first magneticlayer has a pinned magnetic orientation, and wherein said secondmagnetic layer has a free magnetic orientation.
 69. The MRAM device ofclaim 67, wherein said insulator layer comprises a nitride.
 70. The MRAMdevice of claim 67, wherein said barrier layers comprise tantalum. 71.The MRAM device of claim 67, wherein said first conductive layercomprises copper.
 72. The MRAM device of claim 67, wherein said seedlayer comprises nickel iron.
 73. The MRAM device of claim 67, whereinsaid anti-ferromagnetic layer comprises iron manganese.
 74. The MRAMdevice of claim 67, wherein said first magnetic layer comprises nickeliron.
 75. The MRAM device of claim 67, wherein said non-magnetic layercomprises aluminum oxide.
 76. The MRAM device of claim 67, wherein saidtop magnetic layer comprises nickel iron.
 77. The MRAM device of claim67, wherein said second conductive layer comprises copper.
 78. The MRAMdevice of claim 67, wherein said first conductive layer is a bit lineand said second conductive layer is a wordline.
 79. The MRAM device ofclaim 67, further comprising a dielectric layer over said secondconductive layer.
 80. A memory device, comprising: a substrate; aplurality of substantially parallel and spaced insulating structuresabove the uppermost portion of said substrate, each said insulatingstructure comprising sidewalls and a bottom portion between saidsidewalls and being separated by an insulating material which is betweensaid structures and over said substrate; a first barrier layer withinsaid sidewalls and over said bottom portion of said insulatingstructures; a first conductive layer over said first barrier layer andwithin said sidewalls; a second barrier layer over said first conductivelayer and within said sidewalls; a seed layer over said second barrierlayer and within said sidewalls; an anti-ferromagnetic layer over saidseed layer and within said sidewalls; a first magnetic layer over saidanti-ferromagnetic layer and within said sidewalls, said first magneticlayer having an upper recess in a portion thereof; a plurality ofislands over said first magnetic layer, wherein said islands comprise anon-magnetic layer over said first magnetic layer and at least partiallywithin said upper recess, a second magnetic layer over said non-magneticlayer, and a third barrier layer over said second magnetic layer; and asecond conductive layer over each island of said plurality of islands,said second conductive layer being orthogonal to said first magneticlayer.
 81. The memory device of claim 80, wherein said first magneticlayer has a pinned magnetic orientation, and wherein said secondmagnetic layer has a free magnetic orientation.
 82. The memory device ofclaim 80, wherein said sidewalls and said bottom portion of saidplurality of insulating structures comprise a nitride.
 83. The memorydevice of claim 80, wherein said barrier layers comprise tantalum. 84.The memory device of claim 80, wherein said conductive layers comprisecopper.
 85. The memory device of claim 80, wherein said seed layercomprises nickel iron.
 86. The memory device of claim 80, wherein saidanti-ferromagnetic layer comprises iron manganese.
 87. The memory deviceof claim 80, wherein said first magnetic layer comprises nickel iron.88. The memory device of claim 80, wherein said non-magnetic layercomprises aluminum oxide.
 89. The memory device of claim 80, whereinsaid second magnetic layer comprises nickel iron.
 90. The memory deviceof claim 80, wherein said first conductive layer is a digit line andsaid second conductive layer is a sense line.
 91. The memory device ofclaim 80, further comprising a dielectric layer over said secondconductive layer.
 92. An MRAM device, comprising: a pair of nitridesidewalls and a nitride bottom layer between said sidewalls, saidsidewalls and bottom layer being above the uppermost level of anunderlying substrate; a first barrier layer over said nitride bottomlayer and within said nitride sidewalls; a first conductive layer oversaid first barrier layer and within said nitride sidewalls; a secondbarrier layer over said first conductive layer and within said nitridesidewalls; a seed layer over said second barrier layer and within saidnitride sidewalls; an anti-ferromagnetic layer over said seed layer andwithin said sidewalls; a first magnetic layer over saidanti-ferromagnetic layer and within said nitride sidewalls, said firstmagnetic layer having an upper recessed region therein; a non-magneticlayer over a region of said first magnetic layer and within said upperrecessed region of said first magnetic layer; a second magnetic layerover said non-magnetic layer; a third barrier layer over said secondmagnetic layer; and a second conductive layer over said third barrierlayer, said second conductive layer being orthogonal to said firstmagnetic layer.
 93. The MRAM device of claim 92, wherein said barrierlayers comprise tantalum.
 94. The MRAM device of claim 92, wherein saidconductive layers comprises copper.
 95. The MRAM device of claim 92,wherein said seed layer comprises nickel iron.
 96. The MRAM device ofclaim 92, wherein said anti-ferromagnetic layer comprises ironmanganese.
 97. The MRAM device of claim 92, wherein said first magneticlayer comprises nickel iron.
 98. The MRAM device of claim 92, whereinsaid non-magnetic layer comprises aluminum oxide.
 99. The MRAM device ofclaim 92, wherein said second magnetic layer comprises nickel iron. 100.The MRAM device of claim 92, wherein said second conductive layer is asense line and said first conductive layer is a digit line.
 101. TheMRAM device of claim 92, further comprising a dielectric layer over saidsecond conductive layer.
 102. A processor system, comprising: aprocessor; and an MRAM memory circuit coupled to said processor, whereinsaid MRAM memory circuit comprises: an insulator structure having a pairof sidewalls and a bottom portion interconnecting said sidewalls, saidstructure being above an underlying substrate and the uppermost portionthereof; a first conductive layer over said bottom portion and withinsaid sidewalls of said insulator structure; a seed layer over said firstconductive layer and within said sidewalls; an anti-ferromagnetic layerover said seed layer and within said sidewalls; a first magnetic layerover said anti-ferromagnetic layer and within said sidewalls; anon-magnetic layer over a region of said first magnetic layer; a secondmagnetic layer over said non-magnetic layer; and a second conductivelayer over said second magnetic layer and orthogonal to said firstmagnetic layer.
 103. The processor system of claim 102, furthercomprising: a first barrier layer over said bottom portion and withinsaid sidewalls of said insulator structure, wherein said firstconductive layer is over said first barrier layer; a second barrierlayer over said first conductive layer, wherein said seed layer is oversaid second barrier layer; and a third barrier layer over said secondmagnetic layer, wherein said second conductive layer is over said thirdbarrier layer.
 104. The processor system of claim 103, wherein saidfirst magnetic layer comprises an upper recessed region, and saidnon-magnetic layer is within said upper recessed region of said firstmagnetic layer.
 105. The processor system of claim 104, wherein saidsidewalls and said bottom portion of said insulator structure comprise anitride.
 106. The processor system of claim 104, wherein said barrierlayers comprise tantalum.
 107. The processor system of claim 104,wherein said conductive layers comprise copper.
 108. The processorsystem of claim 104, wherein said seed layer comprises nickel iron. 109.The processor system of claim 104, wherein said anti-ferromagnetic layercomprises iron manganese.
 110. The processor system of claim 104,wherein said first magnetic layer comprises nickel iron.
 111. Theprocessor system of claim 104, wherein said non-magnetic layer comprisesaluminum oxide.
 112. The processor system of claim 104, wherein said topmagnetic layer comprises nickel iron.
 113. The processor system of claim104, wherein said second conductive layer is a sense line and said firstconductive layer is a digit line.
 114. The processor system of claim104, further comprising a dielectric layer over said second conductivelayer.
 115. The processor system of claim 104, wherein both theprocessor and the MRAM circuit are integrated on a single chip.
 116. Amethod of forming an MRAM structure comprising: forming a plurality ofspaced longitudinally extending sacrificial regions over an insulatinglayer; forming a plurality of material layers over said insulating layerand said sacrificial regions, the lowermost one of said material layersbeing an insulator layer having a U-shape cross section profile betweensaid spaced sacrificial regions, at least one of said material layersbeing a conductive layer formed over said insulator layer of saidmaterial layers, and at least one of said material layers being amagnetic material layer formed over said conductive layer; and etchingto remove said sacrificial regions and said material layers whereoverlying said sacrificial regions to form a plurality of spaces stackedstructures which include portions of said lowermost insulator layerhaving said U-shape profile, and portions of said conductive and saidmagnetic material layers formed within said U-shaped profile of saidinsulator layer.
 117. The method of claim 116, further comprising:forming a non-magnetic layer over said plurality of spaced stackedstructures and insulating layer; forming a second magnetic layer oversaid non-magnetic layer; removing portions of said non-magnetic layerand said second magnetic layer by etching, leaving islands of saidnon-magnetic layer and said second magnetic layer over regions of saidmagnetic layer of said plurality of spaced stacked structures.